3 BUILDING BLOCKS OF VirtualAnalog™
Our proprietary architectures for traditional analog blocks result in significant power consumption and silicon area reduction.
Our novel calibration schemes enable us to improve performance and alleviate non-idealities in our designs.
Our design methodology leverages powerful digital tools to result in orders of magnitude reduction in design time, and therefore, shrinks the design cycle.
Our customers are leveraging
in a variety of applications
Implement SoCs in unique process
nodes with limited IP infrastructure
Implement analog blocks in low supply
voltages where traditional analog design
approaches break down
Simplify SoC architectures
for better efficiency
Shorten design cycles and get to